1. Technical Field
The present disclosure relates to a display driving technology, and more particularly, to a display driving circuit which is improved to have stability in correspondence to power bouncing and a display device which adopts the display driving circuit.
2. Related Art
A conventional display driving circuit selectively supplies buffered pixel driving signals to output terminals according to an inversion (or polarity inversion) driving scheme. Also, in order to reduce power consumed to buffer the pixel driving signals, the conventional display driving circuit interconnects output terminals for a time during which the pixel driving signals are not applied to a display, and thereby preliminarily drives an output voltage to an intermediate potential.
The conventional display driving circuit includes a plurality of switches for selectively supplying the pixel driving signals to the output terminals or interconnecting the output terminals, and a circuit for controlling the switches. Moreover, the conventional display driving circuit includes level shifters for level-shifting control signals of a low voltage region into control signals of a high voltage region, to appropriately control switches operating in the high voltage region.
FIG. 1 is an exemplary diagram showing the configuration and operations of a level shifter 100 in a conventional display driving circuit.
Referring to (a) of FIG. 1, the level shifter 100 outputs control signals of a high voltage region in correspondence to control signals of a low voltage region. In FIG. 1, a first voltage of the high voltage region is designated by VDD and a second voltage of the high voltage region is designated by VSSH, and a third voltage of the low voltage region is designated by VCC and a fourth voltage of the low voltage region is designated by VSS. The first voltage VDD and the third voltage VCC are used as driving voltages, and the second voltage VSSH and the fourth voltage VSS are used as ground voltages.
The level shifter 100 includes a PMOS network and NMOS transistors M1 and M2. The NMOS transistors M1 and M2 are connected in parallel to the PMOS network. The PMOS network may have, for example, a structure in which PMOS transistors are cross-coupled. The PMOS network and the NMOS transistors M1 and M2 are driven using the first voltage VDD and the second voltage VSSH of the high voltage region.
The control signals driven by the third voltage VCC and the fourth voltage VSS of the low voltage region are applied to the gates of the NMOS transistors M1 and M2. The level shifter 100 outputs control signals SW1 and SW2 of the high voltage region in correspondence to the control signals of the low voltage region.
As described above, the level shifter 100 is driven in the low voltage region, level-shifts the control signals inputted to the NMOS transistors M1 and M2, to the high voltage region, and outputs the control signals SW1 and SW2 of the high voltage region. The level shifter 100 operates by potential differences between the second voltage VSSH and the gates of the NMOS transistors M1 and M2. The potential differences between the gates of the NMOS transistors M1 and M2 and the second voltage VSSH may be designated by VGS, and the threshold voltages of the NMOS transistors M1 and M2 may be designated by VTH.
In detail, the level shifter 100 operates normally when VGS−VTH>0, and does not operate when VGS−VTH<0. In the case where the level shifter 100 does not operate, the control signals SW1 and SW2 outputted from the level shifter 100 become unknown states. In other words, the control signals SW1 and SW2 outputted from the level shifter 100 may correspond to random values regardless of inputs thereto.
In (b) of FIG. 1, the left represents the case where the level shifter 100 operates normally, and the right represents the case where the level shifter 100 operates abnormally.
The conventional display driving circuit has a problem in that the second voltage VSSH related with the control signals bounces as driving current flows by passing through bonding resistance and LOG (line of glass) resistance.
Even though the second voltage VSSH bounces, if the second voltage VSSH bounces to have a potential which is lower by at least a predetermined magnitude than the third voltage VCC of the low voltage region, the level shifter 100 may operate normally. However, if the second voltage VSSH bounces to a level corresponding to VGS−VTH<0, the level shifter 100 operates abnormally.
As a result, the abnormal operation of the level shifter 100 causes the misoperation of the switches included in the display driving circuit, and accordingly, an internal short current path is likely to be formed in the display driving circuit. In this case, the display driving circuit enters an abnormal state, retains the corresponding state, and outputs abnormally the pixel driving signals. Also, the internal short current path may serve as a factor for heat dissipation of the display driving circuit.